1. Field of the Invention
The present invention relates generally to system on chip devices. More particularly, embodiments of the invention relate to a system and method of dynamically scaling a power voltage associated with system on chip devices used in mobile electronics.
2. Discussion of Related Art
System on chip (SoC) technology is widely used in mobile electronic devices to provide fast operational speeds with relatively small power consumption. Dynamic power consumption of a complementary metal oxide semiconductor (CMOS) integrated circuit may be represented by Equation 1:Pd=CL×VDD2×fp,  [Equation 1]where Pd indicates power consumption, CL indicates a capacitance of the integrated circuit, VDD indicates a power supply voltage (hereinafter, it is referred to as a power voltage) provided to the integrated circuit and fp indicates an operational frequency of the integrated circuit. Power consumption is provided in proportion to the capacitance (CL), square of the power voltage (VDD) and the operation frequency (fp). Generally, as the operation frequency (fp) decreases, the power consumption Pd may be decreased. However, semiconductor integrated circuits need to be operated at a high operation frequency (fp) which would increase power consumption Pd.
FIG. 1 is a graph illustrating the relation between power voltage and a maximum operation frequency of a conventional SoC. As the power voltage increases, the maximum operation frequency also increases. FIG. 2 is a graph illustrating the relation between a throughput and a power voltage of a conventional SoC. FIG. 2 illustrates that the power voltage increases when the throughput is large and the power voltage decreases when the throughput is small.
FIG. 3 is a graph illustrating a waveform of a power voltage of a conventional SoC when a target voltage is transmitted. Output voltage VDD of a converter swings between a lower limit voltage and a higher limit voltage in response to target voltage VTARG. Power voltage VDD includes an overshoot voltage VOVSH when target voltage VTARG transitions from a low to a high logic voltage, and power voltage VDD includes an undershoot voltage VUNSH when target voltage VTARG transitions from a high to a low logic voltage. Power voltage VDD drives the SoC and is controlled within a predetermined range. The higher limit voltage is determined based on a hold violation that occurs when the operation speed of the transistors in the SoC is fast. The lower limit voltage is determined based on a setup violation that occurs when the operation speed of the transistors in the SoC is slow. Overshoot voltage VOVSH and undershoot voltage VUNSH are controlled between the higher limit voltage and the lower limit voltage. The overshoot voltage VOVSH and the undershoot voltage VUNSH are increased in proportion to the variation of the target voltage VTARG. Therefore, the overshoot voltage VOVSH and the undershoot voltage VUNSH are decreased by changing the target voltage VTARG step by step.
A clock signal is applied to the SoC based on a gated clock scheme in order to decrease power consumption consumed in several application circuits within the SoC. The gated clock scheme applies clock signals to the application circuit blocks to be activated, and disables clock signals applied to application circuit blocks which are deactivated. The power consumption of the SoC is rapidly increased or rapidly decreased when the clock signals applied to the application circuit blocks are enabled or disabled. A rapid change in the power consumption of the SoC causes a change in the overshoot voltage VOVSH and the undershoot voltage VUNSH of power voltage VDD.
FIG. 4 is a graph illustrating waveforms associated with a power voltage according to changes of a load current and a target voltage in a conventional SoC. The undershoot voltage VUNSH of power voltage VDD results at time T3 when the load current ILOAD transitions from about 10 mA to about 50 mA. The overshoot voltage VOVSH of power voltage VDD results at time T4 when load current ILOAD transitions from about 50 mA to about 10 mA. The load current ILOAD denotes a current of the application circuits in the SoC. In a conventional SoC, the target voltage VTARG and the power voltage VDD are fixed as illustrated in FIG. 4. Thus, target voltage VTARG requires a sufficient voltage margin so as to force power voltage VDD to be greater than the lower limit voltage even though the undershoot voltage VUNSH is generated. The target voltage VTARG is a fixed value, for example, about 1.25V forcing unnecessary power consumption in a conventional SoC. Accordingly, there is a need to suppress the overshoot voltage VOVSH and the undershoot voltage VUNSH when load current ILOAD is changed due to a clock signal transition.